1. Field of the Invention
This invention relates to switched capacitor circuits, and more specifically to methods and apparatus for power reduction in switched capacitor circuits.
2. Background Information
Switched capacitor (SC) circuits are often used in both analog-to-digital convertors (ADC) and in digital-to-analog convertors (DAC) as well as in filters in telecommunication integrated circuits. The basic building blocks of SC-circuits are capacitors, switches and operational amplifiers (opamps). The operational amplifiers are responsible for most of the current consumption in SC-circuits. The operational amplifiers need to be designed so that they can transfer the desired charge between the capacitors through the switches in all conditions during the selected clocking period. The charge transfer requirements in a switched capacitor circuit sets the gain, bandwidth, and slew rate requirements for the operational amplifier. The settling time of the operational amplifier is primarily determined by its bandwidth and slew rate, which determine the current consumption of the operational amplifier. Higher bandwidth and slew rate results in higher current consumption and consequentially higher total power consumption. These requirements are fulfilled for all possible worst case scenarios in simulations, and hence, the opamps are almost always designed for tougher requirements than actually needed. Changing the bias current of the operational amplifier can change the bandwidth and slew rate.
As a switched capacitor circuit is manufactured, there is no perfect control on process conditions, and thus all components in the switched capacitor circuit have statistical variation in their performance. During the design phase, this variation is estimated and thus operational amplifiers are designed so that they meet the settling requirements in the worst-case conditions. Otherwise, the yield can be low. Designing operational amplifiers with the worst-case conditions means high bandwidth and slew rate requirements and thus high power consumption. If the fabricated chip happens to be more average than a worst-case condition chip, extra power is being spent as the switched capacitor circuits on the chip would work with less power and still meet desired performance specifications.
Therefore, a need exists for reducing power in switched capacitor circuits while still keeping the performance of the circuit as close as possible to its maximum.
The present invention is directed to a power reduction device for a switched capacitor circuit that includes a detector and a controller. The detector is connected to both inputs of an operational amplifier in a switched capacitor circuit. The detector monitors the inputs during each clock phase. During every second clock phase a voltage corresponding to full settling (i.e. a zero difference between the inputs) is stored at the end of the clock phase. During the next clock phase the voltage corresponding to the difference between the inputs is compared to the previous value before the end of the clock phase to determine whether it is within the desired range. The controller is connected to an output signal of the detector. The controller adjusts a bias current of the operational amplifier based on the output signal. The bias current is adjusted to as low as possible but just above a value where the comparison falls outside the desired range. The power consumption of the operational amplifier is minimized while a settling time of the operational amplifier is still adequate for maximum performance.
The present invention is also directed to a method for power reduction in a switched capacitor circuit that includes: applying a full bias current level to an operational amplifier; monitoring a settling time of the operational amplifier at the inputs of the operational amplifier; determining if a voltage difference between the inputs is above a threshold; lowering the bias current level for the operational amplifier if the voltage difference between the inputs is below the threshold; repeating the monitoring, determining, and lowering until the voltage difference between the inputs is above the threshold; and setting the bias current level to a previous bias current level before the bias current level where the voltage difference between the inputs is above the threshold. The power consumption of the operational amplifier is minimized while the settling time of the operational amplifier is still adequate for maximum performance.
The present invention is further directed to a power reduction device for a switched capacitor circuit that includes a counter, bias control logic, and a controller. The counter monitors output signals of a switched capacitor circuit. The bias control logic controls a bias current level of at least one operational amplifier in the switched capacitor circuit. The controller is connected to the counter and the bias control logic. The controller sends signals instructing the bias control logic to increase or decrease the bias level current to the at least one operational amplifier based on the accuracy of the monitored output signals. The power consumption of the operational amplifier is minimized while maintaining maximum performance from the operational amplifier.
Moreover, the present invention is directed to a method for power reduction in a switched capacitor circuit that includes: monitoring an output of the switched capacitor circuit; controlling a bias current level of at least one operational amplifier in the switched capacitor circuit; and increasing or decreasing the bias level current to the at least one operational amplifier based on the accuracy of the monitored output signal. The power consumption of the operational amplifier is minimized while maintaining maximum performance from the operational amplifier.